FIG. 17 is a block diagram representing a configuration of a portion related to image display of a conventional portable telephone.
Referring to FIG. 17, the portable telephone includes a control LSI 51, which is an MOST (MOS transistor) type integrated circuit, a level shifter 52, which is an MOST type integrated circuit, and a liquid crystal display device 53, which is a TFT (Thin Film Transistor) type integrated circuit.
Control LSI 51 generates a control signal for liquid crystal display device 53. The “H” level of this control signal is 3V, and the “L” level is 0V. Though a number of control signals are generated actually, only one control signal will be described here for simplicity. Level shifter 52 converts logic level of the control signal from control LSI 51 and generates an internal control signal. The “H” level of this internal control signal is 7.5V and the “L” level is 0V. Liquid crystal display device 53 displays images in accordance with the internal control signal from level shifter 52.
FIG. 18 is circuit diagram representing a configuration of level shifter 52. Referring to FIG. 18,level shifter 52 includes P channel MOS transistors 54, 55 and N channel MOS transistors 56, 57. P channel MOS transistors 54 and 55 are connected between a node N51 of a power supply potential VCC (7.5V) and output nodes N54 and N55, respectively, with their gates connected to output nodes N55 and N54, respectively. N channel MOS transistors 56 and 57 are connected between output nodes N54 and N55 and a node of the ground potential GND, with their gates receiving input signals VI and /VI, respectively.
Assume that the input signals VI and /VI are at the “L” level (0V) and “H” level (3V), respectively, and that the output signals VO and /VO are at the “H” level (7.5V) and the “L” level (0V). At this time, MOS transistors 54 and 57 are conductive, and MOS transistors 55 and 56 are non-conductive.
In this state, when the input signal VI rises from the “L” level (0V) to the “H” level (3V) and the input signal /VI falls from the “H” level (3V) to the “L” level (0V), first, N channel MOS transistor 56 is rendered conductive and the potential at node N54 lowers. When the potential at node N54 becomes lower than a potential that is the power supply potential VCC minus the absolute value of the threshold voltage of P channel MOS transistor 55, P channel MOS transistor 55 is gradually rendered conductive, and the potential at node N55 begins to increase. When the potential at node N55 begins to increase, the source-gate voltage of P channel MOS transistor 54 becomes smaller and the conduction resistance value of P channel MOS transistor 54 becomes higher, and the potential at output node N54 further lowers. Therefore, the circuit operates in a positive feedback manner, and the level converting operation ends when the output nodes VO and /VO attains to the “L” level (0V) and the “H” level (7.5V), respectively.
FIG. 19 is a circuit diagram representing a configuration of another conventional level shifter 60. Referring to FIG. 19, level shifter 60 differs from level shifter 52 shown in FIG. 18 in that P channel MOS transistors 61 and 62 are added. P channel MOS transistor 61 is inserted between the drain of P channel MOS transistor 54 and output node N54, and receives at its gate the input signal VI. P channel MOS transistor 62 is inserted between the drain of P channel MOS transistor 55 and output node N55, and receives at its gate the input signal /VI.
In level shifter 60, when the input signal VI rises from the “L” level (0V) to the “H” level (3V), P channel MOS transistor 61 is rendered from conductive to non-conductive, and the current flowing from node N51 of the power supply potential VCC to output node N54 is reduced, facilitating lowering of the potential at output node N54. As a result, P channel MOS transistor 55 is rendered conductive, facilitating increase of the potential at output node N55. Thus, operation margin becomes larger than level shifter 52 of FIG. 18.
As described above, in the conventional level shifters 52 and 60, it is a presupposition of operation that N channel MOS transistor 56 is rendered conductive in response to the rise of the input signal VI from the “L” level (0V) to the “H” level (3V). In order for N channel MOS transistor 56 to be rendered conductive, it is necessary that the threshold potential of N channel MOS transistor 56 is not higher than the “H” level (3V) of the input signal VI.
In a general semiconductor LSI, the threshold voltage of a transistor can easily be set to 3V or lower. A low-temperature polysilicon TFT that is included in the liquid crystal display device, however, has considerable fluctuation in threshold voltage, and therefore, it is difficult to set the threshold voltage of the TFT at 3V or lower. For this reason, a level shifter 52 or 60 formed by high-breakdown voltage MOS transistors is provided between control LSI 51 and liquid crystal display device 53 to convert logic level of signals.
Provision of such level shifter 52 or 60, however, means addition of cost of the level shifter 52 or 60 to the system cost, resulting in increased system cost.